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Ms. Tarannum Parvin has academic experience of more than 8 years. She has qualified the National Eligibility Test (NET) conducted by the University Grants Commission (UGC). Her research interests include Very Large Scale of Integration (VLSI), VHSIC Hardware Description Language (VHDL), Micro-Electronics and Optimization of Analog & Mixed Signal Integrated Circuits.
Ms. Tarannum Parvin has held various positions of responsibility such as Training & Placement Coordinator and member of e-Office Committee.
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